TOFFEE: a full custom amplifier-comparator chip for timing applications with silicon detectors

We report on the design of a full custom amplifier-comparator readout chip for silicon detectors with internal gain designed for precise timing applications. The ASIC has been developed in UMC 110 nm CMOS technology and is aimed to fulfill the CMS-TOTEM Precision Proton Spectrometer (CT-PPS) time resolution requirements (∼ 30 ps per detector plane). It features LVDS outputs and the signal dynamic range matches the requirements of the High Precision TDC (HPTDC) system. The preliminary measurements results with a test board are included.

: We report on the design of a full custom amplifier-comparator readout chip for silicon detectors with internal gain designed for precise timing applications. The ASIC has been developed in UMC 110 nm CMOS technology and is aimed to fulfill the CMS-TOTEM Precision Proton Spectrometer (CT-PPS) time resolution requirements (∼ 30 ps per detector plane). It features LVDS outputs and the signal dynamic range matches the requirements of the High Precision TDC (HPTDC) system.
The preliminary measurements results with a test board are included.
K : Analogue electronic circuits; Front-end electronics for detector readout; VLSI circuits; Electronic detector readout concepts (solid-state) 1Corresponding author.

Introduction
In the HL-LHC [1] environment, time tagging will be a fundamental tool due to the pile-up of events (∼150-200 per bunch crossing). Time tagging is needed to distinguish events overlapping in space but separated in time by a few tens of picoseconds. In the CMS-TOTEM Precision Proton Spectrometer (CT-PPS) detector [2] of the CMS experiment the reconstruction of the time information will allow to identify the correct interaction vertex by the so called z coordinate (1.1): where t 1 and t 2 are the time of arrival of the two leading protons of the event. By reconstructing the time coordinate with a precision of σ t ∼ 20 ps, it will be possible to determine the z position of the vertex with an accuracy of ∼ 4 mm. The timing capabilities of a sensor-front end system are determined by the characteristics of the signal at the output of the preamplifier and by the TDC binning, according to the formula (1.2) where the first term (noise-to-slope ratio) depends on the noise N and the steepness of the signal dV /dt, the second on the TDC resolution and the third on the sensor signal variations due to non homogeneous charge deposition inside the detector bulk (Landau fluctuations). A charge measurement technique, as Time Over Threshold (TOT), can be used for time walk correction.
In order to improve the time resolution it is required to minimize the noise and to have concurrently large and uniform signals from the detector and a fast readout electronics. The speed of both detector and electronics play a key role in determining the overall time resolution.
In timing applications it is important to minimize the slope-to-noise ratio, which requires electronics with fast peaking time T p . Moreover, the speed of the sensor signal is limiting the shaping time. By considering a sensor signal collecting time T c , an estimate of the resulting amplifier rise time can be T tot = T 2 p + T 2 c . Being the signal slope and the amplifier noise proportional respectively to 1/T tot and 1/ T p , the first contribution to the resolution of formula (1.2) can be approximated as which has a minimum for a peaking time as close as possible to the charge collection time of the sensor [3].

Ultra Fast Silicon Detectors
Ultra Fast Silicon Detectors (UFSD) [4] have been designed with the aim to reconstruct the time coordinate of a particle with a silicon detector. A p + implant (gain layer) below the n ++ electrode produces a high electric field zone which allows multiplying the charge carriers generated by an impinging particle. When crossing the gain layer, electrons multiply via impact ionization mechanism [5] and produce additional electrons and holes (gain electrons and gain holes). The gain electrons are soon collected, while the gain holes drifting to the p ++ electrode generate a large current. UFSD have low gain (∼ 10-20) when compared with similar devices like APDs and allows to keep the multiplication noise low. Low gain also leads to milder electric fields, which makes the electrodes segmentation easier and the overall behavior similar to the one of standard silicon detectors. The signal shape depends on the sensor thickness, in particular the amplitude depends on the gain value while the length on the bulk thickness. For a fixed gain value the signal amplitude is constant while the rise time decreases with decreasing thickness.
A sensor thickness of 50 µm and a gain value of ∼ 15 have been chosen. UFSD current signals have been simulated with the program Weightfield2 [6] and TCAD Synopsys Sentaurus: the typical signal produced by a minimum ionizing particle (MIP) impinging on a 50 µm thick UFSD with a gain of ∼ 15 has a total length of ∼ 1.2 ns [7], delivering a charge of ∼ 8 fC to the amplifier stage.

UFSD for CT-PPS
The UFSD specifically designed for the CMS-TOTEM Precision Proton Spectrometer and produced by CNM (Centro Nacional de Microelectrónica, Barcelona) features a 32 fat strip array with a dead space between strips of 50 µm. In this array, the 16 strips closer to beam line are narrower (3 mm x 0.5 mm) and have a capacitance of 3 pF while the 16 strips further away are wider (3 mm x 1 mm), with a capacitance of 6 pF.
The sensor has a nominal gain of ∼ 15. The signal from each strip will be detected by a DC-coupled front-end mounted close to the detector module inside the PPS roman pot (RP).

TOFFEE design overview
TOFFEE (Time Of Flight Front-End Electronics) is an 8 channels front end ASIC for UFSD read out, designed in standard 110nm CMOS technology. Each channel is independent and the signal processing chain, depicted in figure 1, is composed by: (i) transimpedance amplifier, (ii) single threshold discriminator, (iii) stretcher and (iv) LVDS driver. The High Precision TDC (HPTDC) [8] is a general purpose data driven multi-hit time-to-digital converter. The dead time between hits requires a minimum pulse width to enable the measurement of the leading and trailing edges of the pulse. A stretcher is used to widen the discriminator output in order to produce a pulse wider than 5 ns, as required by HPTDC. TOT technique is used for time walk correction.
The ASIC is optimized for a sensor capacitance of 3-10 pF and an input charge between 3 and 30 fC. The total power budget per channel is less than 30 mW, constrained by termal dissipation in the RPs used for the CT-PPS detector. The output format matches HPTDC inputs through LVDS links (32 pairs per detector module), which consume 10 mW of the power budget per channel.

Preamplifier
The preamplifier (figure 2) is implemented with a telescopic cascode common source amplifier with split bias current and NMOS input transistor. The bias current is provided by two independent branches. The left branch is powering the cascode transistors M3 and M2 with a current properly chosen to meet the desired specs of output swing and slew rate. Taking into account that by reducing this current the output swing increases but the slew rate decreases, appears clear that a trade off is necessary. The value chosen for this current is 200 µA. The right branch delivers a current of ∼ 12 mA to the input transistor M1 and thus the most of the bias current. Thanks to this branch the current can be kept high to increase the transconductance g m1 without reducing the output swing of the stage [3].
The value of the current in transistor M1, its transconductance g m1 and dimensions have been chosen to reach a high gain and a unity-gain-frequency of 14 GHz, to cope with the short collection time T c of the sensor. The power consumption is 14.4 mW, within the specification requirements of less than 20 mW. From the transconductance and the drain-to-source resistance of the transistors of the telescopic cascode it is possible to estimate the DC gain as: in good agreement with simulations results (A v = −255). The amplifier also features resistors for noise degeneration and an output buffer for load driving. The latter is implemented with a source follower with local feedback, in order to maximize the output swing.
Noise analysis. The noise contribution sources of the preamplifier is analyzed in a qualitative way. The three cascode transistors M2, M3 and M5 can be seen as three different source degenerated amplifiers where the degeneration role is played respectively by M1, M4 and M6. Therefore, their equivalent transconductances appear to be negligible if compared with the one of their degeneration transistors making the noise contribution of these devices small [3]. The same concept is applied also to transistors M4 and M6 where the degeneration has been obtained with the use of a couple of resistors as depicted in figure 2. These considerations leads to an expected main contribution due to transistor M1. This is confirmed by simulations results in table 1, in which it is shown that transistor M1 contributes for more than 50% to the total noise of the telescopic cascode.

Discriminator and stretcher
To achieve the highest speed, the discriminator is implemented with a cascade of two stages ( figure 3.a). The total gain of the comparator is then given by the product of the gains of the cascaded stages [3]. The first is a differential pair which further increases the gain of the amplifier, while the second is a single threshold discriminator.   The stretcher is composed of ten consecutive digital delay blocks ( figure 3.b). Each block is formed by an inverter and two starving transistors: the amount of delay added to the signal is tuned by the gate voltage applied to them.
TOFFEE features a preamplifier gain of ∼ 7 mV/fC, a gain-bandwidth of 14 GHz, a RMS noise of ∼ 800 µV (for a detector capacitance of 6 pF) and a power consumption of ∼ 25 mW per channel. The preamplifier is the main contribution to the power consumption of the analog domain (∼ 15 mW), while the discriminator contributes with ∼ 230 µW, being the power dissipated by the digital stretcher negligible. The estimated power consumption of the LVDS driver is ∼ 10 mW.
The ASIC has been received from foundry in September 2016. A sample is shown in figure 4.

Simulations
According to simulations, the preamplifier signal has a peaking time of ∼ 2 ns in schematic and ∼ 3 ns in post-layout simulations and then can be compared the the T c of UFSD sensors. The typical expected charge from the sensors is in the range between 5 and 10 fC.
Simulations have been performed to study the dependency of the Equivalent Noise Charge (ENC) from the detector capacitance. The results, summarized in figure 5.a, show an increase of the ENC for detectors with bigger capacitance as expected. Concerning the jitter, it has been evaluated with post-layout simulations as a function of the input charge. A time resolution of ∼ 45 ps is expected from one single detector for a MIP signal (∼ 8 fC) and a detector capacitance of 6 pF as displayed in figure 5.b. This result can be additionally improved by using more planes in parallel where the time resolution is σ t = jitter N planes (4.1) leading to a ∼ 22 ps time resolution with N planes = 4. The estimated time walk, i.e. the spread of the Time of Arrival (ToA) distribution without ToT correction is ∼ 1.3 ns. With ToT correction we expect a time walk jitter contribution of ∼ 30 ps.

Tests
TOFFEE tests started in October 2016 using a first version of custom boards. These preliminary tests are performed injecting a square input signal to the channels of the chip by using a pulse generator and a RC filter. Amplitude and width have been chosen in order to reproduce the expected sensor signal slew rate whereas the values of R and C are chosen in order to emulate the signal shape of UFSD sensors.
The injected signal has an amplitude of 4.8V, rise and fall times of 2.5 ns, a frequency of 100 kHz and a width of 1.38 µs and is locked to a TTL trigger sent to an oscilloscope. The amplitude allows to maximise the pulser signal-to-noise ratio but this requires the use of a 50 dB attenuator to avoid the preamplifier saturation. The values chosen for the filter are R = 1 kΩ and C = 1 pF, in order to reproduce the charge collection time of the UFSD sensors. A DAC board is used to automatically set the discriminator threshold voltage with a remote computer. A 1 kΩ resistor in series with the DAC output ensures the stability of the DAC board driver.
The LVDS output of TOFFEE is read by a differential probe connected to the oscilloscope, which automatically measures the delay between the trigger signal and the LVDS signal, calculates the average and the standard deviation σ. The noise is evaluated from the slew rate and jitter of the output signal at various threshold values. The measured values, shown in (figure 6.a), are compatible with simulations.
The pulse shape has been reconstructed using the time of arrival and time over threshold measured on the oscilloscope, as shown in figure 6.b. It shows a signal of amplitude 110 mV with peaking time 3 ns, compatible with expectations for the signal of an UFSD with the same charge.
By varying the discriminator threshold voltage it has been possible to measure (i) the signal slew rate dV /dt (ii) the jitter of the TOFFEE + pulse generator system σ = 44 ps and (iii) to evaluate the noise These three values are consistent with simulations.
To measure the ASIC contribution to the total jitter as a function of the input charge the previously described setup has been used. The input charge Q in can be varied by sweeping the pulse amplitude V pulse following the relation Q in = C · V pulse /attenuation. The total jitter read at the oscilloscope (LVDS jitter) comprises the contributions of pulse generator jitter and the one from the ASIC, as shown in figure 7. For a charge of ∼ 12 fC the expected resolution is ∼ 36 ps.

Conclusions and future plans
A full-custom amplifier comparator ASIC have been developed to read-out silicon detectors for timing applications. TOFFEE's amplifier rise-time (∼ 2-3 ns) and slope (> 20 mV/ns) allow minimizing the front-end jitter: according to simulations, for a single TOFFEE-UFSD system the time resolutions is ∼ 45 ps for a typical 8 fC MIP signal and a detector capacitance of 6 pF. The time resolution can be further improved by using more modules in parallel: with 4 modules a resolution of 22 ps can be reached, satisfying the CT-PPS requirements.
The measured time resolution for a ∼ 12 fC signal is ∼ 36 ps. A more reliable measurement needs the use of the real sensors instead of the test pulse. For this reason tests with UFSD sensors + TOFFEE and a new custom board are foreseen for the beginning of 2017.