January 1, 2021 Journal article Closed Access

Andrea Merello; Mirco Di Salvo; Marco Crepaldi

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  "@context": "https://schema.org/", 
  "@id": "https://doi.org/10.1109/access.2021.3104150", 
  "@type": "ScholarlyArticle", 
  "creator": [
    {
      "@type": "Person", 
      "name": "Andrea Merello"
    }, 
    {
      "@type": "Person", 
      "name": "Mirco Di Salvo"
    }, 
    {
      "@type": "Person", 
      "name": "Marco Crepaldi"
    }
  ], 
  "datePublished": "2021-01-01", 
  "description": "This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to enable basic usability in microcontroller applications. The purpose of  ${m}$ OISC is to enable simple data transfer tasks and run small programs while maintaining ultimate simplicity. We present the internal organization for a computer architecture including an 8bit I/O register, and 64kB central Random Access Memory (RAM), organized in two-bytes words. The processor can run code generated assuming an OISC or a Complex Instruction Set Computer (CISC) scheme (op-code based), depending on the programmer&#x2019;s demands and based on the initial setting of a register during start-up. To enable practical applications and demonstrate successful exploitation of  ${m}$ OISC in view of integration in a compiler back-end, we designed a custom Proof-of-Concept (PoC) software design toolchain based on LLVM and clang. Although not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating  ${m}$ OISC code translated from ARM, x86, RISC-V, and MIPS assembly. The toolchain also enables practical Value Change Dump (VCD) simulations output with graphical plots of the CPU state and associated symbols. A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I<sup>2</sup>C) temperature sensor, using its 8bit I/O port, with software bus interface implementation.  ${m}$ OISC occupies &#x007E;6&#x0025; of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers. The measured dynamic current consumption of the complete FPGA board with synthesized  ${m}$ OISC is 12mA at 100MHz clock.", 
  "headline": "A Multi-One Instruction Set Computer for Microcontroller Applications", 
  "identifier": "https://doi.org/10.1109/access.2021.3104150", 
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    "name": "Undetermined"
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  "keywords": [
    "General Engineering", 
    "General Materials Science", 
    "General Computer Science"
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  "license": "https://creativecommons.org/licenses/by/4.0/", 
  "name": "A Multi-One Instruction Set Computer for Microcontroller Applications", 
  "url": "https://www.openaccessrepository.it/record/142349"
}